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| 8 Bit Microcontroller TLCS-870/C Series TMP86CM72FG The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2007 TOSHIBA CORPORATION All Rights Reserved Revision History Date 2007/10/4 Revision 1 First Release Table of Contents TMP86CM72FG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Address Map............................................................................................................................... 9 Program Memory (MaskROM).................................................................................................................. 9 Data Memory (RAM) ................................................................................................................................. 9 Clock Generator...................................................................................................................................... 10 Timing Generator .................................................................................................................................... 12 Operation Mode Control Circuit .............................................................................................................. 13 Single-clock mode Dual-clock mode STOP mode Configuration of timing generator Machine cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 18 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Reset Input ............................................................................................................................... 31 Address trap reset .................................................................................................................................. 32 Watchdog timer reset.............................................................................................................................. 32 System clock reset.................................................................................................................................. 32 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 3.3 3.4 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt acceptance processing is packaged as follows........................................................................ 39 Saving/restoring general-purpose registers ............................................................................................ 40 Interrupt return ........................................................................................................................................ 42 Using PUSH and POP instructions Using data transfer instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 36 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 36 3.4.1 3.4.2 3.4.3 3.5.1 3.5.2 3.4.2.1 3.4.2.2 3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Address error detection .......................................................................................................................... 43 Debugging .............................................................................................................................................. 43 i 3.6 3.7 3.8 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. Program Patch Logic 4.1 4.2 4.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Address jump mode ................................................................................................................................ 50 1-byte data replacement mode ............................................................................................................... 52 2-byte data replacement mode ............................................................................................................... 53 Setting the registers Setting the registers Setting the registers 4.3.1.1 4.3.2.1 4.3.3.1 4.3.1 4.3.2 4.3.3 5. Special Function Register (SFR) 5.1 5.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6. I/O Ports 6.1 6.2 6.3 6.4 6.5 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P52 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports P6 (P67 to P60), P7 (P77 to P70), P8 (P87 to P80), and P9 (P97 to P90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 66 67 69 70 7. Watchdog Timer (WDT) 7.1 7.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 72 73 74 74 75 7.3 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 76 76 76 77 7.3.1 7.3.2 7.3.3 7.3.4 8. Time Base Timer (TBT) 8.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Configuration .......................................................................................................................................... 79 Control .................................................................................................................................................... 79 8.1.1 8.1.2 ii 8.2 8.1.3 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Configuration .......................................................................................................................................... 81 Control .................................................................................................................................................... 81 Function .................................................................................................................................................. 80 8.2.1 8.2.2 9. 16-Bit Timer/Counter2 (TC2) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timer mode............................................................................................................................................. 85 Event counter mode................................................................................................................................ 87 Window mode ......................................................................................................................................... 87 9.3.1 9.3.2 9.3.3 10. 8-Bit TimerCounter 3 (TC3) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.3.1 Timer mode........................................................................................................................................... 92 Figure 10-3 ...................................................................................................................................................... 94 10.3.3 Capture Mode ....................................................................................................................................... 95 11. 8-Bit TimerCounter 4 (TC4) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Timer Mode........................................................................................................................................... 99 Event Counter Mode ........................................................................................................................... 100 Programmable Divider Output (PDO) Mode ....................................................................................... 101 Pulse Width Modulation (PWM) Output Mode .................................................................................... 102 11.3.1 11.3.2 11.3.3 11.3.4 12. Synchronous Serial Interface (SIO) 12.1 12.2 12.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Serial clock ......................................................................................................................................... 108 Transfer bit direction ........................................................................................................................... 110 Transfer modes................................................................................................................................... 110 Transmit mode Transmit error Receive mode Receive error Transmit/receive mode Transmit/receive error MSB transfer LSB transfer Clock source Shift edges 12.3.1.1 12.3.1.2 12.3.2.1 12.3.2.2 12.3.3.1 12.3.3.2 12.3.3.3 12.3.3.4 12.3.3.5 12.3.3.6 12.3.1 12.3.2 12.3.3 12.4 Chip selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 iii 13. Asynchronous Serial interface (UART ) 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 130 Data Receive Operation ..................................................................................................................... 130 131 131 131 132 132 133 125 126 128 129 129 130 130 130 13.8.1 13.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 13.9.1 13.9.2 13.9.3 13.9.4 13.9.5 13.9.6 14. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 14.1 14.2 14.3 14.4 14.5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Data Format in the I2C Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgement mode specification................................................................................................ 139 Number of transfer bits ....................................................................................................................... 140 Serial clock ......................................................................................................................................... 140 Clock source Clock synchronization Acknowledgment mode (ACK = "1") Non-acknowledgment mode (ACK = "0") 14.5.1.1 14.5.1.2 135 135 135 136 137 14.5.1 14.5.2 14.5.3 14.6 14.5.4 14.5.5 14.5.6 14.5.7 14.5.8 14.5.9 14.5.10 14.5.11 14.5.12 14.5.13 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.5.3.1 14.5.3.2 Data Transfer of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Device initialization ............................................................................................................................. 145 Start condition and slave address generation..................................................................................... 145 1-word data transfer............................................................................................................................ 145 Stop condition generation ................................................................................................................... 148 Restart ................................................................................................................................................ 149 When the MST is "1" (Master mode) When the MST is "0" (Slave mode) Slave address and address recognition mode specification ............................................................... Master/slave selection ........................................................................................................................ Transmitter/receiver selection............................................................................................................. Start/stop condition generation ........................................................................................................... Interrupt service request and cancel................................................................................................... Setting of I2C bus mode ..................................................................................................................... Arbitration lost detection monitor ...................................................................................................... Slave address match detection monitor............................................................................................ GENERAL CALL detection monitor .................................................................................................. Last received bit monitor................................................................................................................... 141 141 141 142 142 143 143 144 144 144 14.6.3.1 14.6.3.2 15. 8-Bit AD Converter (ADC) 15.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 iv 15.2 15.3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 AD Conveter Operation ...................................................................................................................... AD Converter Operation ..................................................................................................................... STOP and SLOW Mode during AD Conversion ................................................................................. Analog Input Voltage and AD Conversion Result ............................................................................... 154 154 155 156 15.4 15.3.1 15.3.2 15.3.3 15.3.4 15.4.1 15.4.2 15.4.3 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Analog input pin voltage range ........................................................................................................... 157 Analog input shared pins .................................................................................................................... 157 Noise countermeasure........................................................................................................................ 157 16. Key-on Wakeup (KWU) 16.1 16.2 16.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 17. Vacuum Fluorescent Tube (VFT) Driver Circuit 17.1 17.2 17.3 17.4 17.5 17.6 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Example of Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Port Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 High-breakdown voltage buffer ........................................................................................................... 170 Caution ............................................................................................................................................... 170 When outputting When inputting Ports P6 to P9 17.3.1 17.3.2 Setting of Display mode ...................................................................................................................... 166 Display data setting ............................................................................................................................ 166 17.5.1 17.5.2 17.6.1 17.6.2 For Conventional type VFT ................................................................................................................. 168 For Grid scan type VFT ...................................................................................................................... 169 17.6.1.1 17.6.2.1 17.6.2.2 18. Input/Output Circuitry 18.1 18.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Input/Output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 19. Electrical Characteristics 19.1 19.2 19.3 19.4 19.5 19.6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 How to Calculate Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 AD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 DC Characteristics (1) (VDD = 5 V) .................................................................................................... 178 DC Characteristics (2) (VDD = 3 V) .................................................................................................... 179 19.3.1 Power consumption Pmax = Operating power consumption + Normal output port loss + VFT driver loss. ............................................................................................ 177 19.4.1 19.4.2 v 19.7 HSIO AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Note 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 19.8 19.9 Note 2: Note 2: Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ........................................................................................................................................................... 182 ........................................................................................................................................................... 182 20. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). vi TMP86CM72FG CMOS 8-Bit Microcontroller TMP86CM72FG Product No. ROM (MaskROM) 32768 bytes RAM 1024 bytes Package OTP MCU Emulation Chip TMP86CM72FG QFP64-P-1414-0.80C TMP86PM72FG TMP86C972XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 19interrupt sources (External : 6 Internal : 13) 3. Input / Output ports (54 pins) Large current output: 2pins (Typ. 20mA), LED direct drive 4. Watchdog Timer 5. Prescaler - Time base timer - Divider output function 6. 16-bit timer counter: 1 ch - Timer, Event counter, Window modes 7. 8-bit timer counter : 1 ch - Timer, Event counter, Capture modes 8. 8-bit timer counter : 1 ch - Timer, Event counter, Pulse width modulation (PWM) output, Programmable divider output (PDO) modes 9. Serial Interface - 8-bit SIO :1 channel (32 bytes Buffer) * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86CM72FG 10. 8-bit UART : 1 ch 11. Serial Bus Interface(I2C Bus): 1ch 12. 8-bit successive approximation type AD converter (with sample hold) Analog inputs: 6ch 13. Key-on wakeup : 4 ch 14. Vacuum flouorescent tube driver (automatic display) - Programmable grid scan - High breakdown voltage ports(MAX 40 V x 37 bits) 15. Clock operation Single clock mode Dual clock mode 16. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz Release by Page 2 TMP86CM72FG 1.2 Pin Assignment (V14) P76 (V13) P75 (V12) P74 (V11) P73 (V10) P72 (V9) P71 (V8) P70 (V7) P67 (V6) P66 (V5) P65 (V4) P64 (V3) P63 (V2) P62 (V1) P61 (V0) P60 VDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P77 (V15) P80 (V16) P81 (V17) P82 (V18) P83 (V19) P84 (V20) P85 (V21) P86 (V22) P87 (V23) P90 (V24) P91 (V25) P92 (V26) P93 (V27) P94 (V28) P95 (V29) P96 (V30) VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Figure 1-1 Pin Assignment Page 3 (TC2/INT5/STOP) P20 (TC3/INT3) P10 (TC4/PWM4/PDO4) P11 (TXD) P12 (RXD/INT2) P13 (SDA/SI) P14 (SCL/SO) P15 (SCK) P16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P97(V31) VKK VAREF P47(AIN5/STOP5) P46(AIN4/STOP4) P45(AIN3/STOP3) P44(AIN2/STOP2) P43(AIN1) P42(AIN0) AVSS P41 P40 P52(INT1) P51(INT0) P50(DVO) P17(CS/INT4) 1.3 Block Diagram TMP86CM72FG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86CM72FG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/3) Pin Name P17 CS Pin Number Input/Output IO I I IO IO IO O O IO I I IO I I IO O IO O I IO I I PORT17 SIO chip select input External interrupt 4 input PORT16 Serial clock input/output PORT15 Serial data output I2C bus clock PORT14 Serial data input I2C bus data PORT13 External interrupt 2 input UART data input PORT12 UART data output PORT11 PWM4/PDO4 output TC4 input PORT10 External interrupt 3 input TC3 pin input Functions 17 INT4 P16 SCK 16 P15 SO SCL P14 SI SDA P13 INT2 RXD P12 TXD P11 PWM4/PDO4 15 14 13 12 11 TC4 P10 INT3 TC3 10 P22 XTOUT 7 IO O PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock PORT20 STOP mode release signal input External interrupt 5 input TC2 input PORT47 AD converter analog input 5 STOP5 input PORT46 AD converter analog input 4 STOP4 input PORT45 AD converter analog input 3 STOP3 input PORT44 AD converter analog input 2 STOP2 input PORT43 AD converter analog input 1 PORT42 AD converter analog input 0 P21 XTIN 6 IO I P20 STOP INT5 9 TC2 P47 AIN5 STOP5 P46 AIN4 STOP4 P45 AIN3 STOP3 P44 AIN2 STOP2 P43 AIN1 P42 AIN0 IO I I I IO I I IO I I IO I I IO I I IO I IO I 29 28 27 26 25 24 Page 5 1.4 Pin Names and Functions TMP86CM72FG Table 1-1 Pin Names and Functions(2/3) Pin Name P41 P40 P52 INT1 P51 INT0 Pin Number 22 21 Input/Output IO IO IO I IO I IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O PORT41 PORT40 PORT52 External interrupt 1 input PORT51 External interrupt 0 input PORT50 Divider Output PORT67 Grid output7 PORT66 Grid output6 PORT65 Grid output5 PORT64 Grid output4 PORT63 Grid output3 PORT62 Grid output2 PORT61 Grid output1 PORT60 Grid output0 PORT77 Grid output15 PORT76 Grid output14 PORT75 Grid output13 PORT74 Grid output12 PORT73 Grid output11 PORT72 Grid output10 PORT71 Grid output9 PORT70 Grid output8 PORT87 Segment output23 PORT86 Segment output22 PORT85 Segment output21 Functions 20 19 P50 DVO 18 P67 V7 P66 V6 P65 V5 P64 V4 P63 V3 P62 V2 P61 V1 P60 V0 P77 V15 P76 V14 P75 V13 P74 V12 P73 V11 P72 V10 P71 V9 P70 V8 P87 V23 P86 V22 P85 V21 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 Page 6 TMP86CM72FG Table 1-1 Pin Names and Functions(3/3) Pin Name P84 V20 P83 V19 P82 V18 P81 V17 P80 V16 P97 V31 P96 V30 P95 V29 P94 V28 P93 V27 P92 V26 P91 V25 P90 V24 XIN XOUT RESET Pin Number Input/Output IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O I O I I I I I I PORT84 Segment output20 PORT83 Segment output19 PORT82 Segment output18 PORT81 Segment output17 PORT80 Segment output16 PORT97 Segment output31 PORT96 Segment output30 PORT95 Segment output29 PORT94 Segment output28 PORT93 Segment output27 PORT92 Segment output26 PORT91 Segment output25 PORT90 Segment output24 Functions 43 44 45 46 47 32 33 34 35 36 37 38 39 2 3 8 4 30 23 5 1 Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test. Normally, be fixed to low. Analog reference voltage input (High) AD circuit power supply Power Supply 0V(GND) TEST VAREF AVSS VDD VSS Page 7 1.4 Pin Names and Functions TMP86CM72FG Page 8 TMP86CM72FG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86CM72FG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the memory address map. TMP86CM72FG 0000H SFR: SFR 003FH 0040H 64 bytes RAM 043FH 1024 bytes RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack 0F80H DBR: DBR 0FFFH 128 bytes Data buffer register includes: Peripheral control registers Peripheral status registers 8000H MaskROM: Program memory MaskROM FFC0H FFDFH FFE0H FFFFH 32768 bytes Vector table for vector call instructions (32 bytes) Vector table for interrupts (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (MaskROM) The TMP86CM72FG has a 32768 bytes (Address 8000H to FFFFH) of program memory (MaskROM ). 2.1.3 Data Memory (RAM) The TMP86CM72FG has 1024bytes (Address 0040H to 043FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. Page 9 2. Operational Description 2.2 System Clock Controller TMP86CM72FG The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to "00H". (TMP86CM72FG) LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 03FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 10 TMP86CM72FG High-frequency clock XIN XOUT XIN XOUT (Open) XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 11 2. Operational Description 2.2 System Clock Controller TMP86CM72FG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 fc or fs Main system clock generator SYSCK DV7CK Machine cycle counters High-frequency clock fc Low-frequency clock fs 12 fc/4 S A 123456 B Y Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 12 TMP86CM72FG Timing Generator Control Register TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86CM72FG is placed in this mode after reset. Page 13 2. Operational Description 2.2 System Clock Controller TMP86CM72FG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 (3) SLOW1 mode This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Page 14 TMP86CM72FG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 (4) IDLE2 mode In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. (5) SLEEP1 mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode. In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (6) SLEEP2 mode The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock. (7) SLEEP0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by setting "1" on bit SYSCR2 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 15 2. Operational Description 2.2 System Clock Controller TMP86CM72FG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate Stop Halt Halt STOP NORMAL2 IDLE2 Oscillation SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Halt Halt Halt - Oscillation Operate with low frequency Halt Operate with low frequency Operate 4/fs [s] Operate Stop Operate with high frequency Halt Halt - Operate 4/fc [s] Machine Cycle Time RESET NORMAL1 Oscillation Single clock IDLE1 IDLE0 Reset Operate Reset 4/fc [s] Page 16 TMP86CM72FG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W RELM R/W RETM R/W OUTEN R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN High-frequency oscillator control 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W XTEN Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) R/W SYSCK IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 17 2. Operational Description 2.2 System Clock Controller TMP86CM72FG 2.2.4 Operating Mode Control STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5ASTOP2) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 2.2.4.1 Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5ASTOP2). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5ASTOP2 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5 STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP5ASTOP2 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2PRD). 0 F, SSTOPH ; IMF 0 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Page 18 TMP86CM72FG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2PRD). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 ; Starts STOP mode STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP5ASTOP2 pin input for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF 0 ; Starts after specified to the edge-sensitive release mode STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode Page 19 2. Operational Description 2.2 System Clock Controller TMP86CM72FG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 20 Turn off Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 21 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86CM72FG 2. Operational Description 2.2 System Clock Controller TMP86CM72FG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Interrupt request Yes "0" IMF Reset Normal release mode "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 22 TMP86CM72FG * Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 (1) Normal release mode (IMF = "0") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions. (2) Interrupt release mode (IMF = "1") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 23 Main system clock 2.2 System Clock Controller 2. Operational Description Interrupt request a+2 SET (SYSCR2). 4 Operate Halt a+3 Program counter Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request a+3 Instruction address a + 2 Operate Normal release mode a+4 Program counter Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24 a+3 Acceptance of interrupt Operate Operate Interrupt release mode Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Watchdog timer Halt TMP86CM72FG (b) IDLE1/2 and SLEEP1/2 modes release TMP86CM72FG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 25 2. Operational Description 2.2 System Clock Controller TMP86CM72FG * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (1) Normal release mode (IMF*EF7*TBTCR (2) Interrupt release mode (IMF*EF7*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 26 Main system clock Interrupt request a+2 a+3 Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE and SLEEP0 modes release TMP86CM72FG Watchdog timer Halt 2. Operational Description 2.2 System Clock Controller TMP86CM72FG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LDW DI SET EI SET : PINTTC2: CLR SET (TC2CR). 5 (SYSCR2). 5 ; Stops TC2 ; SYSCR2 Page 28 TMP86CM72FG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD DI SET EI SET : PINTTC2: CLR CLR (TC2CR). 5 (SYSCR2). 5 ; Stops TC2 ; SYSCR2 Page 29 2.2 System Clock Controller 2. Operational Description Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86CM72FG SLOW1 mode NORMAL2 mode TMP86CM72FG 2.3 Reset Circuit The TMP86CM72FG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 RAM Refer to each of control register Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 31 2. Operational Description 2.3 Reset Circuit TMP86CM72FG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Internal reset JP a Address trap is occurred Reset release Instruction at address r maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR, DBR or on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 Page 32 TMP86CM72FG Page 33 2. Operational Description 2.3 Reset Circuit TMP86CM72FG Page 34 TMP86CM72FG 3. Interrupt Control Circuit The TMP86CM72FG has a total of 19 interrupt sources excluding reset, of which 3 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Factors Internal/External Internal Internal Internal Internal External Internal External Internal Internal Internal Internal Internal External External Internal Internal External Internal External (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1, INT0EN = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1, IL9ER = 0 IMF* EF9 = 1, IL9ER = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1, IL14ER = 0 IMF* EF14 = 1, IL14ER = 1 IMF* EF15 = 1, IL15ER = 0 IMF* EF15 = 1, IL15ER = 1 Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC Priority 1 2 2 2 2 5 6 7 8 9 10 INTRXD INT1 INTTBT INTTC3 INTSIO INTI2C INTTC4 INT3 INT4 INTTXD INTTC2 INT5 IL10 IL11 IL12 IL13 IL14 FFEA FFE8 FFE6 FFE4 FFE2 11 12 13 14 15 INTADC INT2 IL15 FFE0 16 Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Page 35 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CM72FG Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". 3.2.2 Individual interrupt enable flags (EF15 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor- Page 36 TMP86CM72FG mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 37 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CM72FG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) IL15 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) EF15 to EF4 Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. R/W Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts IMF Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 38 TMP86CM72FG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INTSIO and INTI2C share the interrupt source level whose priority is 10. 2. INTTC2 and INT5 share the interrupt source level whose priority is 15. 3. INTADC and INT2 share the interrupt source level whose priority is 16. Interrupt source selector INTSEL (003EH) 7 6 IL9ER 5 4 3 2 1 IL14ER 0 IL15ER (Initial value: *0** **00) IL9ER Selects INTSIO or INTI2C 0: INTSIO 1: INTI2C 0: INTTC2 1: INT5 0: INTADC 1: INT2 R/W IL14ER Selects INTTC2 or INT5 R/W IL15ER Selects INTADC or INT2 R/W 3.4 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Page 39 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CM72FG 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF0H FFF1H 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. Page 40 TMP86CM72FG 3.4.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.4.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Page 41 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CM72FG Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Page 42 TMP86CM72FG Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.5.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR or SFR areas. 3.5.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.6 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.7 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 3.8 External Interrupts The TMP86CM72FG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/p51 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/p51 pin function selection are performed by the external interrupt control register (EINTCR). Page 43 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CM72FG Source Pin Enable Conditions Release Edge (level) Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF6 = 1 Falling edge or Rising edge INT2 INT2 IMF EF15 = 1 and IL15ER=1 Falling edge or Rising edge INT3 INT3 IMF EF11 = 1 Falling edge or Rising edge INT4 INT4 IMF EF12 = 1 Falling edge, Rising edge, Falling and Rising edge or H level INT5 INT5 IMF EF14 = 1 and IL14ER=1 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 44 TMP86CM72FG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 INT4ES 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 0000 000*) INT1NC Noise reject time select 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: p51 input/output port 1: INT0 pin (Port p51 should be set to an input mode) 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: H level 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W INT0EN p51/INT0 pin configuration R/W INT4 ES INT4 edge select R/W INT3 ES INT3 edge select R/W INT2 ES INT2 edge select R/W INT1 ES INT1 edge select R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. Page 45 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CM72FG Page 46 TMP86CM72FG 5. Special Function Register (SFR) The TMP86CM72FG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86CM72FG. 5.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H SBISRB TC2DRL TC2DRH UARTSR RDBUF SBIDBR I2CAR SBICRB SIOSR SIOBUF UARTCR1 UARTCR2 TDBUF SBICRA P1PRD P2PRD Reserved TC4DR SIOCR1 SIOCR2 TC3DRB TC3CR TC2CR TC4CR Read Reserved P1DR P2DR Reserved P4DR P5DR P6DR P7DR P8DR P9DR Reserved P1OUTCR P4CR1 P5CR ADCCR1 ADCCR2 TC3DRA Write Page 57 5. Special Function Register (SFR) 5.1 SFR TMP86CM72FG Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read ADCDR2 ADCDR1 P4CR2 TC3SEL VFTCR1 VFTCR2 VFTCR3 VFTSR Reserved ROMCCR Reserved Reserved Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH INTSEL PSW Write - - STOPCR WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 58 TMP86CM72FG 5.2 DBR Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH 0F8DH 0F8EH 0F8FH 0F90H 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH Read VFTDBR(T0,V7 to V0) VFTDBR(T1,V7 to V0) VFTDBR(T2,V7 to V0) VFTDBR(T3,V7 to V0) VFTDBR(T4,V7 to V0) VFTDBR(T5,V7 to V0) VFTDBR(T6,V7 to V0) VFTDBR(T7,V7 to V0) VFTDBR(T8,V7 to V0) VFTDBR(T9,V7 to V0) VFTDBR(T10,V7 to V0) VFTDBR(T11,V7 to V0) VFTDBR(T12,V7 to V0) VFTDBR(T13,V7 to V0) VFTDBR(T14,V7 to V0) VFTDBR(T15,V7 to V0) VFTDBR(T0,V15 to V8) VFTDBR(T1,V15 to V8) VFTDBR(T2,V15 to V8) VFTDBR(T3,V15 to V8) VFTDBR(T4,V15 to V8) VFTDBR(T5,V15 to V8) VFTDBR(T6,V15 to V8) VFTDBR(T7,V15 to V8) VFTDBR(T8,V15 to V8) VFTDBR(T9,V15 to V8) VFTDBR(T10,V15 to V8) VFTDBR(T11,V15 to V8) VFTDBR(T12,V15 to V8) VFTDBR(T13,V15 to V8) VFTDBR(T14,V15 to V8) VFTDBR(T15,V15 to V8) Write Page 59 5. Special Function Register (SFR) 5.2 DBR TMP86CM72FG Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H 0FB7H 0FB8H 0FB9H 0FBAH 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH Read VFTDBR(T0,V23 to V16) VFTDBR(T1,V23 to V16) VFTDBR(T2,V23 to V16) VFTDBR(T3,V23 to V16) VFTDBR(T4,V23 to V16) VFTDBR(T5,V23 to V16) VFTDBR(T6,V23 to V16) VFTDBR(T7,V23 to V16) VFTDBR(T8,V23 to V16) VFTDBR(T9,V23 to V16) VFTDBR(T10,V23 to V16) VFTDBR(T11,V23 to V16) VFTDBR(T12,V23 to V16) VFTDBR(T13,V23 to V16) VFTDBR(T14,V23 to V16) VFTDBR(T15,V23 to V16) VFTDBR(T0,V31 to V24) VFTDBR(T1,V31 to V24) VFTDBR(T2,V31 to V24) VFTDBR(T3,V31 to V24) VFTDBR(T4,V31 to V24) VFTDBR(T5,V31 to V24) VFTDBR(T6,V31 to V24) VFTDBR(T7,V31 to V24) VFTDBR(T8,V31 to V24) VFTDBR(T9,V31 to V24) VFTDBR(T10,V31 to V24) VFTDBR(T11,V31 to V24) VFTDBR(T12,V31 to V24) VFTDBR(T13,V31 to V24) VFTDBR(T14,V31 to V24) VFTDBR(T15,V31 to V24) Write Page 60 TMP86CM72FG Address 0FC0H 0FC1H 0FC2H 0FC3H 0FC4H 0FC5H 0FC6H 0FC7H 0FC8H 0FC9H 0FCAH 0FCBH 0FCCH 0FCDH 0FCEH 0FCFH 0FD0H 0FD1H 0FD2H 0FD3H 0FD4H 0FD5H 0FD6H 0FD7H 0FD8H 0FD9H 0FDAH 0FDBH 0FDCH 0FDDH 0FDEH 0FDFH Read RCAD0L RCAD0H RCDT0L RCDT0H RCAD1L RCAD1H RCDT1L RCDT1H RCAD2L RCAD2H RCDT2L RCDT2H RCAD3L RCAD3H RCDT3L RCDT3H Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Write Address 0FE0H :: 0FFFH Read Reserved :: Reserved Write Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 61 5. Special Function Register (SFR) 5.2 DBR TMP86CM72FG Page 62 TMP86CM72FG 6. I/O Ports The TMP86CM72FG has 8 parallel input/output ports (54 pins) as follows. Primary Function Port P1 8-bit I/O Secondary Functions External interrupt input, timer/counter input/output, Serial interface input/output Low-frequency resonator connections, external interrupt input/output, STOP mode release signal Input Analog input, STOP mode release signal input External interrupt input, DVO output VFT output VFT output VFT output VFT output Port P2 Port P4 Port P5 Port P6 Port P7 Port P8 Port P9 3-bit I/O 8-bit I/O 3-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 6-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle S0 Instruction execution cycle S1 S2 S3 Fetch cycle S0 S1 S2 S3 S0 Read cycle S1 S2 S3 Ex: LD A, (x) Input strobe Data input (a) Input timing Fetch cycle S0 Instruction execution cycle S1 S2 S3 Fetch cycle S0 S1 S2 (x), A S3 S0 Write cycle S1 S2 S3 Ex: LD Output latch pulse Data output Old New (b) Output timing Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 6-1 Input/Output Timing (Example) Page 63 6. I/O Ports 6.1 Port P1 (P17 to P10) TMP86CM72FG 6.1 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port, and also used as a timer counter input/output, external interrupt input, and serial interface input/output. To use port P1 as an input port or secondary function pins, set its output latch (P1DR) to "1". A reset sets the output latch to "1" and clears the push-pull control register (P1OUTCR) to "0". The P1OUTCR can be used to select sink open-drain output or CMOS output for the output circuit of port P1. To use port P1 as an input port, set the P1DR to "1", and then clear the corresponding bit of the P1OUTCR to "0". Port P1 has separate data input registers. To sense the state of the output latch, read the P1DR. To sense the state of the pins the port, read the P1 port input data (P1PRD) register. The input waveform of a TC3 input can be inverted in terms of phase, using the Timer Counter3 input control (TC3SEL) register. P10, P11, P12, and P13 can work not only as a port but also as, respectively, the TC3/INT3, PWM4/PDO4/TC4, TXD, and RXD/INT2 functions. To use the TC3, INT3, TC4, RXD and INT2 functions, place the respective pins in input mode. To use the PWM4 and PDO4 functions, place the respective pins in output mode. P14, P15, P16, and P17 can work not only as a port but also as, respectively, the SI/SDA, SO/SCL, SCK, and CS/ INT4 functions. To use these functions, place the pin corresponding to the SI, CS, and INT4 function in input mode, the pin corresponding to the SO, SDA, and SCL function in output mode (when using it in I2C bus, it is used by sink open-drain output.), and the pin corresponding to the SCK function in either input or output mode. STOP OUTEN P1OUTCRi P1OUTCRi input Data input (P1PRD) Data input (P1DR) Data output (P1DR) Control output TC3INV TC3INV input Control input(TC3) Control input (except for TC3, CS) Control input (CS) D Q For P11 only D Q D Q P1i Note: i = 7 to 0 Noise canceller Figure 6-2 Port P1 Page 64 TMP86CM72FG 7 P1DR (0001H) R/W P17 CS 6 P16 SCK 5 P15 SO SCL 4 P14 SI SDA 3 P13 RXD INT2 2 P12 TXD 1 P11 PWM4 PDO4 0 P10 TC3 INT3 INT4 (Initial value: 1111 1111) TC4 P1OUTCR (000BH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P1OUTCR I/O control for port P1 (This register can be set on bit basis.) 0: Sink open drain 1: CMOS output R/W P1PRD (0015H) Read only TC3SBI (0029H) 7 6 5 4 3 2 1 0 7 CSEN 6 5 SBISEL 4 3 2 1 0 TC3INV (Initial value: 0*0* ***0) TC3INV TC3 input control 0: Normal input 1: Inverted input 0: SIO (P15: SO pin) 1: I2C (P15: SCL pin) 0: Disable 1: Enable R/W SBISEL SIO/I2C BUS selection (P15) CSEN Chip enable function control P1OUTCR 0 0 1 1 P1DR 0 1 0 1 Function Low output Input, open-drain output, or control input Low output High output or control output Page 65 6. I/O Ports 6.2 Port P2 (P22 to P20) TMP86CM72FG 6.2 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. It can work not only as a port but also as external input, STOP mode release signal input, and low-frequency resonator connection pins. To use it as an input port or the secondary function pins, set the output latch (P2DR) to "1". A reset initializes the P2DR to "1". To run the device in dual clock mode, connect a low-frequency resonator (32.768 kHz) to pins P21 (XTIN) and P22 (XTOUT). When the device runs in single clock mode, P21 and P22 can be used as an ordinary input/output port. It is recommended that pin P20 be used for external interrupt input, STOP release signal input, or as an input port (if it is used as an output port, it is set with the content of the interrupt latch at the negative-going edge of the signal). Port P2 has separate data input registers. To sense the state of the output latch, read the P2DR. To sense the state of the pins of the port, read the P2 port input data (P2PRD) register. If a read instruction is executed for the P2DR or P2PRD on port P2, the sensed state of bits 7 to 3 is undefined. Data input (P20) Data output (P20) Data input (P20PRD), Control input Data input (P21PRD) Data input (P21) Data output (P21) Data input (P22PRD) Data input (P22) Data output (P22) STOP OUTEN XTEN fs DQ Output latch Osc. enable DQ Output latch DQ Output latch P20 (INT5, STOP) P21 (XTIN) P22 (XTOUT) Figure 6-3 Port P2 7 P2DR (0002H) R/W 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 0 P20 INT5 STOP (Initial value: **** *111) P2PRD (0016H) Read only 7 6 5 4 3 2 1 0 Note: Because pin P20 is used also as the STOP pin, its output high impedance becomes high when it enters the STOP mode regardless of the state of OUTEN. Page 66 TMP86CM72FG 6.3 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port. Each bit of the port can be configured for either input or output separately, using the P4 port input/output control register (P4CR1). These pins can work not only as a port but also for analog input and key-on-wakeup input. To use each bit for output, set the corresponding bit of the P4CR1 to "1" to place them in output mode. To use them in input mode, clear the corresponding bit of the P4CR1 to "0", then set the P4CR2 to "1". To use the bits for analog input and key-on-wakeup input, clear the P4CR1 and P4CR2 to "0" in the stated order (then, for analog input, clear the ADCCR1 Key-on-wakeup Analog input AINDS SAIN P4CR2i P4CR2i input P4CR1i P4CR1i input Data input (P4DR) Data output (P4DR) OUTEN STOP STOPj P44, P45, 46, 47 P42, 43, 44, 45, 46, 47 D Q Note 1: i = 7 to 0, and j = 5 to 2 Note 2: STOP is SYSCR1 bit 7. Note 3: SAIN is an AD input selection signal. Note 4: STOPj is an input selection signal for the key-on wakeup function. D Q D Q P4i Figure 6-4 Port P4 Page 67 6. I/O Ports 6.3 Port P4 (P47 to P40) TMP86CM72FG 7 P4DR (0004H) R/W P4CR1 (000CH) P47 AIN5 STOP5 7 6 P46 AIN4 STOP4 6 5 P45 AIN3 STOP3 5 4 P44 AIN2 STOP2 4 3 P43 AIN1 2 P42 AIN0 1 P41 0 P40 (Initial value: 0000 0000) 3 2 1 0 (Initial value: 0000 0000) P4CR1 I/O control for port P4 (This register can be set on bit basis.) 0: Input mode or analog input/key-on wakeup input 1: Output mode R/W P4CR2 (0028H) 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) P4CR2 (Bit 7 to 2) I/O control for port P4 (This register can be set on bit basis.) I/O control for port P4 (This register can be set on bit basis.) 0: Analog input/key-on wakeup input 1: Input mode R/W P4CR2 (Bit 1, 0) 0: Sink open drain output 1: CMOS output Note 1: If a port is in input mode, it senses the state of an input to its pins. If some pins of the port are in input mode, and others are in output mode, the content of the output latch related to a port pin that is in input mode may be changed when a bit manipulation instruction is executed on the port. Note 2: The P4CR2 controls the input gate of pins used for analog input. In analog input mode, clear the P4CR2 to "0" to fix the input gate, thereby protecting it from through current. In input mode, set the P4CR2 to "1". When using the key-on wakeup function, clear the P4CR2 to "0", because the inputs are received separately. If the P4CR2 is "0", read accessing the P4CR2 yields "0". Page 68 TMP86CM72FG 6.4 Port P5 (P52 to P50) Port P5 is a 3-bit general-purpose input/output port. Each bit of the port can be configured for either input or output separately, using the P5 port input/output control register (P5CR). A reset clears the P5CR to "0", placing port P5 in input mode. A reset also initializes the P5 port output latch (P5DR) to "0". P51, and P52 can work not only as an input/output port but also, respectively, for the INT0, and INT1 functions. To use these functions, place the corresponding pins in input mode. P50 can work not only as a port but also as, respectively, the DVO function. To use the DVO function, place the respective pin in output mode. STOP OUTEN P5CRi P5CRi input Data input (P5DR) Data output (P5DR) Control output Control input D Q P5i Note: i = 3 to 0 D Q Figure 6-5 Port P5 7 P5DR (0005H) 6 5 4 3 2 P52 INT1 1 P51 INT0 0 P50 DVO (Initial value: **** *000) P5CR (000DH) 7 6 5 4 3 2 1 0 (Initial value: **** *000) P5CR I/O control for port P5 (This register can be set on bit basis.) 0: Input mode 1: Output mode R/W Note: If a port is in input mode, it senses the state of an input to its pins. If some pins of the port are in input mode, and others are in output mode, the content of the output latch related to a port pin that is in input mode may be changed when a bit manipulation instruction is executed on the port. Page 69 6. I/O Ports 6.5 Ports P6 (P67 to P60), P7 (P77 to P70), P8 (P87 to P80), and P9 (P97 to P90) TMP86CM72FG 6.5 Ports P6 (P67 to P60), P7 (P77 to P70), P8 (P87 to P80), and P9 (P97 to P90) Ports P6, P7, P8, and P9 are 8-bit high-breakdown voltage input/output ports. They can work not only as a port but also for VFT driver output. They can drive directly a vacuum fluorescent tube (VFT). To use them as an input port or VFT driver, clear the output latch to "0". Pins not set up for VFT driver output can be used as an input/output port. To use a pin for ordinary input/output when a VFT driver is used, clear the VFT driver output data buffer memory (DBR) for the pin to "0". A reset initializes the output latch to "0". It is recommended that ports P6, P7, P8, and P9 be used to drive a VFT because they have a built-in pull-down resistor. CMP/MCMP/TEST/Others Data input Data output VFT driver output STOP OUTEN SET/CLR/CPL/Others Output latch D Q VKK Figure 6-6 Port P6, P7, P8, and P9 P6i P7i P8i P9i Note: i = 7 to 0 P6DR (0006H) R/W P7DR (0007H) R/W P8DR (0008H) R/W P9DR (0009H) R/W 7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 (Initial value: 0000 0000) 7 P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 P71 0 P70 (Initial value: 0000 0000) 7 P87 6 P86 5 P85 4 P84 3 P83 2 P82 1 P81 0 P80 (Initial value: 0000 0000) 7 P97 6 P96 5 P95 4 P94 3 P93 2 P92 1 P91 0 P90 (Initial value: 0000 0000) Page 70 TMP86CM72FG 7. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 7-1 Watchdog Timer Configuration Page 71 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CM72FG 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 72 TMP86CM72FG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "7.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 7.2.2 Watchdog Timer Enable Setting WDTCR1 Page 73 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CM72FG 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary counter : WDTEN 0, WDTCR2 Disable code Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 7.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 043FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 74 TMP86CM72FG 7.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 7-2 Watchdog Timer Interrupt Page 75 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CM72FG 7.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is required) 0: Interrupt request 1: Reset request Write only ATOUT Select operation at address trap Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 7.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 7.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 7.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 76 TMP86CM72FG 7.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 77 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CM72FG Page 78 TMP86CM72FG 8. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 8.1 Time Base Timer 8.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 8-1 Time Base Timer configuration 8.1.2 Control Time Base Timer is controlled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - R/W - - - - - TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 79 8. Time Base Timer (TBT) 8.1 Time Base Timer TMP86CM72FG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 7 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 8-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 8.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generator which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 8-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 8-2 Time Base Timer Interrupt Page 80 TMP86CM72FG 8.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 8.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 8-3 Divider Output 8.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 81 8. Time Base Timer (TBT) 8.2 Divider Output (DVO) TMP86CM72FG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 8-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 82 TMP86CM72FG 9. 16-Bit Timer/Counter2 (TC2) 9.1 Configuration TC2S H Window TC2 pin Port (Note) 23, 15 fc/2 fs/2 fc/213, fs/25 fc/28 fc/23 fc fs A B C D E F S 3 TC2CK B Timer/ event counter Clear Y A S Source clock 16-bit up counter TC2M TC2S TC2CR TC2DR 16-bit timer register 2 CMP Match INTTC2 interrupt TC2 control register Note: When control input/output is used, I/O port setting should be set correctly. For details, refer to the section "I/O ports". Figure 9-1 Timer/Counter2 (TC2) Page 83 9. 16-Bit Timer/Counter2 (TC2) 9.2 Control TMP86CM72FG 9.2 Control The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). TC2DR (0025H, 0024H) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2DRH (0025H) (Initial value: 1111 1111 1111 1111) TC2DRL (0024H) R/W TC2CR (0013H) 7 6 5 TC2S 4 3 TC2CK 2 1 0 TC2M (Initial value: **00 00*0) TC2S TC2 start control 0:Stop and counter clear 1:Start NORMAL1/2, IDLE1/2 mode Divider DV7CK = 0 000 001 fc/223 fc/213 fc/28 fc/2 - fs 3 R/W SLOW1/2 mode fs/215 fs/25 - - fc (Note7) - SLEEP1/2 mode fs/215 fs/25 - - - - R/W DV7CK = 1 fs/215 fs/25 fc/28 fc/2 - fs 3 DV21 DV11 DV6 DV1 - - TC2CK TC2 source clock select Unit : [Hz] 010 011 100 101 110 111 Reserved External clock (TC2 pin input) R/W TC2M TC2 operating mode select 0:Timer/event counter mode 1:Window mode Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side (TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect. Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper side (TC2DRH) after writing data to the lower side (TC2DRL). Note 4: Set the mode and source clock when the TC2 stops (TC2S = 0). Note 5: Values to be loaded to the timer register must satisfy the following condition. TC2DR > 1 (TC2DR15 to TC2DR11 > 1 at warm up) Note 6: If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable. Note 7: The high-frequency clock (fc) canbe selected only when the time mode at SLOW2 mode is selected. Note 8: On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC2S again. Page 84 TMP86CM72FG 9.3 Function The timer/counter 2 has three operating modes: timer, event counter and window modes. And if fc or fs is selected as the source clock in timer mode, when switching the timer mode from SLOW1 to NORMAL2, the timer/counter2 can generate warm-up time until the oscillator is stable. 9.3.1 Timer mode In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. When fc is selected for source clock at SLOW2 mode, lower 11-bits of TC2DR are ignored and generated a interrupt by matching upper 5-bits only. Though, in this situation, it is necessary to set TC2DRH only. Table 9-1 Source Clock (Internal clock) for Timer/Counter2 (at fc = 16 MHz, DV7CK=0) TC2C K NORMAL1/2, IDLE1/2 mode SLOW1/2 mode DV7CK = 0 DV7CK = 1 Maximum Time Setting 18.2 [h] 1.07 [min] - - - - Maximum Time Setting 18.2 [h] 1.07 [min] - - - - SLEEP1/2 mode Resolution Maximum Time Setting Resolution Maximum Time Setting Resolution Resolution 000 001 010 011 100 101 524.29 [ms] 512.0 [ms] 16.0 [ms] 0.5 [ms] - 30.52 [ms] 9.54 [h] 33.55 [s] 1.05 [s] 32.77 [ms] - 2 [s] 1 [s] 0.98 [ms] 16.0 [ms] 0.5 [ms] - 30.52 [ms] 18.2 [h] 1.07 [min] 1.05 [s] 32.77 [ms] - 2 [s] 1 [s] 0.98 [ms] - - 62.5 [ns] - 1 [s] 0.98 [ms] - - - - Note:When fc is selected as the source clock in timer mode, it is used at warm-up for switching from SLOW1 mode to NORMAL2 mode. Example :Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25 ms (at fc = 16 MHz ) LDW DI SET EI LD LD (TC2CR), 00001000B (TC2CR), 00101000B (EIRH). 6 (TC2DR), 061AH ; Sets TC2DR (25 ms 28/fc = 061AH) ; IMF= "0" ; Enables INTTC2 interrupt ; IMF= "1" ; Source clock / mode select ; Starts Timer Page 85 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function TMP86CM72FG Timer start Source clock Up-counter 0 1 2 3 4 Match detect n0 1 2 3 Counter clear TC2DR INTTC2 interrupt Figure 9-2 Timer Mode Timing Chart Page 86 TMP86CM72FG 9.3.2 Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. Counting up is resumed every the rising edge of the TC2 pin input after the up counter is cleared. Match detect is executed on the falling edge of the TC2 pin. Therefore, an INTTC2 interrupt is generated at the falling edge after the match of TC2DR and up counter. The minimum input pulse width of TC2 pin is shown in Table 9-2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Example :Sets the event counter mode and generates an INTTC2 interrupt 640 counts later. LDW DI SET EI LD LD (TC2CR), 00011100B (TC2CR), 00111100B (EIRH). 6 (TC2DR), 640 ; Sets TC2DR ; IMF= "0" ;Enables INTTC2 interrupt ; IMF= "1" ; TC2 source vclock / mode select ; Starts TC2 Table 9-2 Timer/Counter 2 External Input Clock Pulse Width Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 mode "H" width "L" width 23/fc 23/fc SLOW1/2, SLEEP1/2 mode 23/fs 23/fs Timer start TC2 pin input Counter 0 1 2 3 Match detect n 0 1 2 3 Counter clear TC2DR n INTTC2 interrupt Figure 9-3 Event Counter Mode Timing Chart 9.3.3 Window mode In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input (Window pulse) is "H" level. The contents of TC2DR are compared with the contents of up counter. If a match found, an INTTC2 interrupt is generated, and the up-counter is cleared. The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock by the TC2CR Note:It is not available window mode in the SLOW/SLEEP mode. Therefore, at the window mode in NORMAL mode, the timer should be halted by setting TC2CR Page 87 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function TMP86CM72FG Example :Generates an interrupt, inputting "H" level pulse width of 120 ms or more. (at fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC2CR), 00000101B (TC2CR), 00100101B (EIRH). 6 (TC2DR), 00EAH ; Sets TC2DR (120 ms 213/fc = 00EAH) ; IMF= "0" ; Enables INTTC2 interrupt ; IMF= "1" ; TC2sorce clock / mode select ; Starts TC2 Timer start TC2 pin input Internal clock Counter TC2DR Match detect INTTC2 interrupt Counter clear 1 2 n 0 1 2 3 Figure 9-4 Window Mode Timing Chart Page 88 TMP86CM72FG 10.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB). Timer Register and Control Register TC3DRA (0010H) TC3DRB (0011H) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) Read only (Initial value: 1111 1111) TC3CR (0012H) 7 6 ACAP 5 4 TC3S 3 2 TC3CK 1 0 TC3M (Initial value: *0*0 0000) ACAP Auto capture control 0: - 1: Auto capture 0: Stop and counter clear 1: Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 fc/213 fc/212 fc/211 fc/210 fc/29 fc/28 fc/2 7 R/W TC3S TC3 start control R/W SLOW1/2, SLEEP1/2 mode fs/25 fs/24 fs/23 fs/22 fs/2 - - R/W DV7CK = 1 fs/25 fs/24 fs/23 fs/22 fs/2 fc/28 fc/2 7 Divider DV11 DV10 DV9 DV8 DV7 DV6 DV5 TC3CK TC3 source clock select [Hz] 010 011 100 101 110 111 External clock (TC3 pin input) R/W TC3M TC3 operating mode select 0: Timer/event counter mode 1: Capture mode Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: Set the operating mode and source clock when TimerCounter stops (TC3S = 0). Note 3: To set the timer registers, the following relationship must be satisfied. TC3DRA > 1 (Timer/event counter mode) Note 4: Auto-capture (ACAP) can be used only in the timer and event counter modes. Note 5: When the read instruction is executed to TC3CR, the bit 5 and 7 are read as a don't care. Note 6: Do not program TC3DRA when the timer is running (TC3S = 1). Note 7: When the STOP mode is entered, the start control (TC3S) is cleared to 0 automatically, and the timer stops. After the STOP mode is exited, TC3S must be set again to use the timer counter. TimerCounter 3 Input Control Register TC3SEL (0029H) 7 6 5 4 3 2 1 0 TC3INV Read/Write (Initial value: **** ***0) Event counter mode TC3INV TC3 input control 0: 1: Count at the rising edge Count at the falling edge Capture mode An interrupt is generated at the rising edge. An interrupt is generated at the falling edge. R/W Note: When the read instruction is executed to TC3SEL, the bit 7 to 1 are read as a don't care. Page 91 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP86CM72FG 10.3 Function TimerCounter 3 has three types of operating modes: timer, event counter and capture modes. 10.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 3A (TC3DRA) value is detected, an INTTC3 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC3CR Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Clock TC3DRA Up-counter Match detect C8 C6 C7 C8 00 01 TC3DRB C6 C7 C8 01 Note: In the case that TC3DRB is C8H Figure 10-2 Auto-Capture Function Table 10-1 Source Clock for TimerCounter 3 (Example: fc = 16 MHz, fs = 32.768 kHz) TC3CK DV7CK = 0 Resolution [s] 000 001 010 011 100 101 110 512 256 128 64 32 16 8 Maximum Time Setting [ms] 130.6 65.3 32.6 16.3 8.2 4.1 2.0 Resolution [s] 976.56 488.28 244.14 122.07 61.01 16.0 8.0 NORMAL1/2, IDLE1/2 mode DV7CK = 1 Maximum Time Setting [ms] 249.0 124.5 62.3 31.1 15.6 4.1 2.0 SLOW1/2, SLEEP1/2 mode Resolution [s] 976.56 488.28 244.14 122.07 61.01 - - Maximum Time Setting [ms] 249.0 124.5 62.3 31.1 15.6 - - Page 92 TMP86CM72FG Timer start Source clock Counter 0 1 2 3 4 n0 1 2 3 4 5 6 7 TC3DRA INTTC3 interrupt ? n Match detect Counter clear (a) Timer mode Source clock Counter m m+1 m+2 n n+1 Capture TC3DRB ? m m+1 m+2 n Capture n+1 TC3CR Figure 10-3 Timer Mode Timing Chart Page 93 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP86CM72FG 10.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC3 pin. Either the rising or falling edge of the input pulse is programmed as the count up edge in TC3SEL Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Example :Inputting 50 Hz pulse to TC3, and generating interrupts every 0.5 s LD LD LD LD (TC3SEL), 00000000B (TC3CR), 00001110B (TC3DRA), 19H (TC3CR), 00011110B : Selects the count-up edge. : Sets the clock mode : 0.5 s / 1/50 = 25 = 19H : Starts TC3. Table 10-2 Maximum Frequencies Applied to TC3 Minimum Pulse Width NORMAL1/2, IDLE1/2 mode High-going Low-going 22/fc 22/fc SLOW1/2, SLEEP1/2 mode 22/fs 22/fs Timer start TC3 pin input Counter 0 1 2 3 n Match detect 0 1 2 3 Counter clear TC3DRA INTTC3 interrupt n Figure 10-4 Event Counter Mode Timing Chart (TC3SEL Page 94 TMP86CM72FG 10.3.3 Capture Mode In the capture mode, the pulse width, frequency and duty cycle of the pulse input to the TC3 pin are measured with the internal clock. The capture mode is used to decode remote control signals, and identify AC50/60 Hz. Either the rising or falling edge is programmed in TC3SEL TC3SEL Rising edge Falling edge The minimum input pulse width must be larger than one cycle width of the source clock programmed in TC3CR Page 95 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP86CM72FG Timer start TC3CR When TC3DRA is not read, capture operation and overflow detection are stopped. 0 1 i-1 i i+1 k-1 k0 1 m-1 m m+1 n-1 n 0 1 2 3 FE FF 0 1 2 3 k Capture i Capture m Capture n Capture FE FF (Overflow) Overflow 0 1 i-1 i 0 1 k-1 k0 k-1 m-1 m 0 m+1 n-3 n-2 n-1 n0 3 FE FF 0 1 2 3 Figure 10-5 Capture Mode Timing Chart Page 96 TMP86CM72FG 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TC4S fc/211 or fs/23 fc/27 fc/25 fc/23 fc/22 fc/2 fc (Note) A B Source C Clock Clear D EY Y 8-bit up-counter F G H S 3 CMP Overflow detect 0 1 Match detect S Y TC4 pin Timer F/F TC4CK Toggle Port (Note) TC4S TC4M 2 0 Y 1 Clear S PWM output mode PWM4/ PDO4/ pin TC4CR TC4DR TC4S INTTC4 interrupt PDO mode Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 11-1 TimerCounter 4 (TC4) Page 97 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86CM72FG 11.2 TimerCounter Control The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and timer registers 4 (TC4DR). Timer Register and Control Register TC4DR (0018) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) TC4CR (0014) 7 6 5 TC4S 4 3 TC4CK 2 1 TC4M 0 Read/Write (Initial value: **00 0000) TC4S TC4 start control 0: Stop and counter clear 1: Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 fc/211 fc/27 fc/25 fc/23 fc/22 fc/2 fc DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fc/22 fc/2 fc External clock (TC4 pin input) Divider SLOW1/2, SLEEP1/2 mode fs/23 - - - - - - R/W DV9 DV5 DV3 DV1 - - - TC4CK TC4 source clock select [Hz] 010 011 100 101 110 111 R/W TC4M TC4 operating mode select 00: Timer/event counter mode 01: Reserved 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: To set the timer registers, the following relationship must be satisfied. 1 TC4DR 255 Note 3: To start timer operation (TC4S = 0 1) or disable timer operation (TC4S = 1 0), do not change the TC4CR Timer Mode 000 001 010 TC4CK 011 100 101 110 111 O O O O - - - - Event Counter Mode - - - - - - - O PDO Mode O O O - - - - - PWM Mode - - - O O O O x Note: O : Available source clock Page 98 TMP86CM72FG 11.3 Function TimerCounter 4 has four types of operating modes: timer, event counter, programmable divider output (PDO), and pulse width modulation (PWM) output modes. 11.3.1 Timer Mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Table 11-1 Source Clock for TimerCounter 4 (Example: fc = 16 MHz, fs = 32.768 kHz) NORMAL1/2, IDLE1/2 Mode TC4CK DV7CK = 0 DV7CK = 1 SLOW1/2, SLEEP1/2 Mode Maximum Time Setting [ms] 62.2 - - - Resolution [s] Maximum Time Setting [ms] Resolution [s] Maximum Time Setting [ms] Resolution [s] 000 001 010 011 128.0 8.0 2.0 0.5 32.6 2.0 0.510 0.128 244.14 8.0 2.0 0.5 62.2 2.0 0.510 0.128 244.14 - - - Page 99 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86CM72FG 11.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4 pin. Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC4DR. The minimum pulse width applied to the TC4 pin are shown in Table 11-2. The pulse width larger than two machine cycles is required for high- and low-going pulses. Note:The event counter mode can not used in the SLOW1/2 and SLEEP1/2 modes since the external clock is not supplied in these modes. Table 11-2 External Source Clock for TimerCounter 4 Minimum Pulse Width NORMAL1/2, IDLE1/2 mode High-going Low-going 23/fc 23/fc Page 100 TMP86CM72FG 11.3.3 Programmable Divider Output (PDO) Mode The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state and INTTC4 interrupt request is generated. The up-counter is cleared at this time and then counting is continued. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state again and INTTC4 interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued. When the timer is stopped, the PDO4 pin is high. Therefore, if the timer is stopped when the PDO4 pin is low, the duty pulse may be shorter than the programmed value. Example :Generating 1024 Hz pulse (fc = 16.0 Mhz) LD LD LD (TC4CR), 00000110B (TC4DR), 3DH (TC4CR), 00100110B : Sets the PDO mode. (TC4M = 10, TC4CK = 001) : 1/1024 / 27/fc / 2 (half cycle period) = 3DH : Start TC4 Internal clock Counter 0 1 2 n0 1 2 n0 1 2 n0 1 2 n0 1 TC4DR n Match detect Timer F/F PDO4 pin INTTC4 interrupt request Figure 11-2 PDO Mode Timing Chart Page 101 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86CM72FG 11.3.4 Pulse Width Modulation (PWM) Output Mode The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of resolution by an internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PWM4 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM4 pin becomes high. The INTTC4 interrupt request is generated at this time. When the timer is stopped, the PWM4 pin is high. Therefore, if the timer is stopped when the PWM4 pin is low, one PMW cycle may be shorter than the programmed value. TC4DR is serially connected to the shift register. If TC4DR is programmed during PWM output, the data set to TC4DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically. For the first time, the data written to TC4DR is shifted when the timer is started by setting TC4CR Note 1: The PWM output mode can be used only in the NORMAL1/2 and IDEL 1/2 modes. Note 2: In the PWM output mode, program TC4DR immediately after the INTTC4 interrupt request is generated (typically in the INTTC4 interrupt service routine.) When the programming of TC4DR and the INTTC4 interrupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is issued. TC4CR Internal clock Counter 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m Rewrite TC4DR ? n m Rewrite p Rewrite Data shift m Data shift Shift register ? n Data shift Match detect Timer F/F Match detect Match detect PWM4 pin INTTC4 interrupt request n n m PWM cycle Figure 11-3 PWM output Mode Timing Chart (TC4) Page 102 TMP86CM72FG Table 11-3 PWM Mode (Example: fc = 16 MHz) NORMAL1/2, IDLE1/2 Mode TC4CK DV7CK = 0 Resolution [ns] 000 001 010 011 100 101 110 - - - 500 250 125 - Cycle [s] - - - 128 64 32 - Resolution [ns] - - - 500 250 125 - DV7CK = 1 Cycle [s] - - - 128 64 32 - Page 103 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86CM72FG Page 104 TMP86CM72FG 12. Synchronous Serial Interface (SIO) The TMP86CM72FG contain one SIO (synchronous serial interface) channel. It is connected to external devices via the SI, SO and SCK pins. The SI pin is used also as the P14 pin, the SO pin is used also as the P15 pin, and the SCK pin is used also as the P16 pin. The CS pin is used also as the P17 pin, CS pin can be used as a chip selection function (at external clock input mode). Using these pins for serial interfacing requires setting the output latches of the each port to "1". SIO Functions. * Transfer mode (8 bit) * Receive mode (8 bit) * Transfer/Receive mode (8 bit) * Internal /External clock selection * 32 bytes Buffer conbining Transfer and Receive Table 12-1 lists the SIO1 register addresses. Table 12-1 Control Registers SIO1 Register name SIO control register 1 SIO control register 2 SIO status register SIO data buffer SIOCR1 SIOCR2 SIOSR SIOBUF Address 0019H 001AH 001BH 001CH 12.1 Configuration SIO buffer SCK fc/2 or fs/2 13 5 SIOCR1 SIOSR SIOCR2 Buffer control A B C D E F G H Y fc/28 fc/26 fc/25 fc/24 fc/23 fc/22 Transmit shift register Shift clock Control circuit MSB/LSB selection Chihp select Receive shift register SCK pin serial clock input/output Noise canceller CS pin Chip select input SO pin serial data output SI pin serial data input External clock CSEN TC3SBI control circuit INTSIO interrupt Figure 12-1 Configuration of the Serial Interface Page 105 12. Synchronous Serial Interface (SIO) 12.2 Control TMP86CM72FG 12.2 Control SIO is controlled using Serial Interface Control Register 1 (SIOCR1) and Serial Interface Control Register 2 (SIOCR2). The operating status of the serial interface can be determined by reading the Serial Interface Status Register (SIOSR). Serial Interface Control Register 1 SIOCR1 (0019H) 7 SIOS 6 SIONH 5 SIOM 4 3 SIODIR 2 1 SCK 0 (Initial value: 0000 0000) SIOS Start/Stop a transfer. Continue/Abort a transfer (Note 1) 0: Stop 1: Start 0: Continue transfer. 1: Abort transfer (automatically cleared after abort). 00: Transmit mode 01: Receive mode 10: Transmit/receive mode 11: Reserved 0: MSB (transfer beginning with bit 7) 1: LSB (transfer beginning with bit 0) NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 010 fc/213 fc/28 fc/26 fc/2 5 SIOINH SIOM Select transfer mode. SIODIR Select direction of transfer DV7CK = 1 fs/25 fc/28 fc/26 fc/2 5 Source clock DV11 DV6 DV4 DV3 DV2 DV1 fc/2 2 SLOW1/2, SLEEP1/2 mode fs/25 - - - - - - R/W SCK Select a serial clock. (Note 2) 011 100 101 110 fc/24 fc/2 fc/2 3 2 fc/24 fc/2 fc/2 3 2 111 External clock (supplied from the SCK pin) External clock (supplied from the SCK pin) - - Note 1: If SIOCR1 Page 106 TMP86CM72FG Serial Interface Control Register 2 SIOCR2 (001AH) 7 "0" 6 "0" 5 "0" 4 3 2 SIORXD 1 0 (Initial value: ***0 0000) SIORXD Set the number of data bytes to transmit/receive. 00H: 1-byte transfer 01H: 2-byte transfer 02H: 3-byte transfer 03H: 4-byte transfer : 1FH: 32-byte transfer R/W Note 1: Before setting the number of data bytes to transfer, make sure the SIO is idle (SIOSR Serial Interface Status Register SIOSR (001BH) 7 SIOF 6 SEF 5 TXF 4 RXF 3 TXERR 2 RXERR 1 0 (Initial value: 0010 00**) SIOF Monitor the operating status of serial transfer. Shift operation status flag 0: Transfer ended (Note1) 1: Transfer in process 0: Shift ended 1: Shift in process 0: The transmit buffer contains data. 1: The transmit buffer contains no data. 0: The receive buffer contains no data. 1: As many data bytes specified in SIORXD have been received. (The flag is reset to "0" when as many data bytes as specified in SIORXD have been read.) 0: Transmit operation was normal. 1: Error occurred during transmission. 0: Receive operation was normal. 1: Error occurred during reception. Read only SEF TXF Transmit buffer flag RXF Receive buffer flag TXERR Transmit error flag (Note2) RXERR Receive error flag (Note2) Note 1: The SIOSR Serial Interface Data Buffer SIOBUF (001CH) 7 6 5 4 3 2 1 0 (Initial value: **** ****) SIOBUF Transmit/receive data buffer Transmit data are set, or received data are stored. R/W Note 1: Setting SIOCR1 Page 107 12. Synchronous Serial Interface (SIO) 12.3 Function TMP86CM72FG 12.3 Function 12.3.1 Serial clock 12.3.1.1 Clock source One of the following clocks can be selected using SIOCR1 (1) Internal clock A clock having the frequency selected with SIOCR1 Table 12-2 Serial Clock Rate Baud Rate SCK Clock fc = 16 MHz 000 001 010 011 100 101 110 111 fc/213 fc/28 fc/26 fc/25 fc/24 fc/23 fc/22 External 1.91 Kbps 61.04 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps - - External fc = 8 MHz 0.95 Kbps 30.51 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps - External (1 Kbit = 1,024 bit) (2) External clock Setting SIOCR1 SCK pin is used as the serial clock. For a shift operation to be performed securely, both the high and low levels of the serial clock pulse must be at least 4/fc. If fc = 8 MHz, therefore, the maximum available transfer rate is 976.56 Kbps. SCK pin input tSCKL tSCKL, tSCKH tSCKL, tSCKH tSCKH 2.5/fc (High-frequency clock mode 2.5/fs (Low-frequency clock mode) Figure 12-2 External Clock Page 108 TMP86CM72FG 12.3.1.2 Shift edges The SIO uses leading-edge shift for transmission and trailing-edge shift for reception. (1) Leading-edge shift Data are shifted on each leading edge of the serial clock pulse (falling edge of the SCK pin input/ output). (2) Trailing-edge shift Data are shifted on each trailing edge of the serial clock pulse (rising edge of the SCK pin input/ output). SCK pin SO pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Shift register *******7 ******76 *****765 ****7654 ***76543 **765432 *7654321 76543210 (a) Leading-edge shift SCK pin SI pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Shift register *******7 ******76 *****765 ****7654 ***76543 **765432 *7654321 76543210 (b) Trailing-edge shift Figure 12-3 Shift Edges Page 109 12. Synchronous Serial Interface (SIO) 12.3 Function TMP86CM72FG 12.3.2 Transfer bit direction The direction in which 8-bit serial data are transferred can be selected using SIOCR1 12.3.2.1 MSB transfer MSB transfer is assumed by clearing SIOCR1 12.3.2.2 LSB transfer LSB transfer is assumed by setting SIOCR1 SCK pin A7 A A6 A5 A4 A3 A2 A1 A0 SCK pin A7 A6 A5 A4 A3 A2 A1 A0 A SO pin Transmitdata write SI pin Receiveddata store (a) MSB transfer (when SIODIR = "0" SCK pin A0 A A1 A2 A3 A4 A5 A6 A7 SCK pin A0 A1 A2 A3 A4 A5 A6 A7 A SO pin Transmitdata write SI pin Receiveddata store (b) LSB transfer (when SIODIR = "1" Figure 12-4 Transfer Bit Direction 12.3.3 Transfer modes SIOCR1 12.3.3.1 Transmit mode Transmit mode is assumed by setting SIOCR1 (1) Causing the SIO to start transmitting 1. Set the transmit mode, serial clock rate, and transfer direction, respectively, in SIOCR1 TMP86CM72FG 4. SIOCR1 (2) Causing the SIO to stop transferring 1. When as many data bytes as specified in SIOCR2 Second last byte SCK pin A0 B7 B6 B5 Last byte SO pin B4 B3 B2 B1 B0 SIOS SIOS = "0" causes the SIO to stop transferring. SIOF SEF TXF INTSIO is accepted. INTSIO TSODH (16.5/fc to 32.5/fc) 6.5 TSCK + TSODH Figure 12-5 Time from INTSIO Occurrence to Transfer End (SIOSR Note 1: Be sure to write as many bytes as specified in SIOCR2 Page 111 12. Synchronous Serial Interface (SIO) 12.3 Function TMP86CM72FG SIOS SCK pin SIOF Last bit of transmit data TSODH If transmission is completed after SIOS is cleared 16.5/fc TSODH 32.5/fc SO pin fc: High-frequency clock [Hz] Figure 12-6 Last-Bit Hold Time * Setting SIOCR1 SIOS = "0" causes the SIO to stop transferring. SIOS SIOF SEF SCK pin SO pin A7 A6 C0 D7 D6 D5 D4 D3 D2 D1 D0 TXF INTSIO Clearing SIOS within the interrupt service routine Figure 12-7 SIOCR1 12.3.3.2 Transmit error During operation on an external clock, the following case may be detected as a transmit error, causing the transmit error flag (SIOSR Page 112 TMP86CM72FG Example :Example of setting the transmit mode (transmit mode, external clock, and 32-byte transfer) Port setting (It is necessary to set P15 as SOpin by port setting. LD DI LD LDW EI LD WAIT: TEST JRS (SIOCR1), 01******B (SIOSR). 7 F, WAIT (INTSEL),*0******B (EIRL), ******1********0B (TC3SBI),**0*****B ) ; IMF 0 ; INTSIO Select ; Enables INTSIO (EF9). ; Enables interrupts. ; Initializes the SIO (forces the SIO halt). ; Checks to see if the SIO has halted (SIOF = 0). ; Jumps to START if the SIO is already at a halt. ; Sets the transmit mode, selects the direction of transfer, and sets a serial clock. ; Sets the number of bytes (32 bytes) to transfer. START: LD (SIOCR1), 00000111B LD (SIOCR2), 00011111B : Transmit data setting : LD INTSIO (INTSIO service routine): LD TEST JRS LD (SIOCR1), 10000111B ; Directs the SIO to start transferring. (SIOCR1), 00000111B (SIOSR). 3 T, NOERR (SIOCR1), 01000111B : Error handling : ; Directs the SIO to stop transferring. ; Checks TXERR. ; Forces the SIO to halt (clears TXERR). NOERR: END: ; End of transfer Page 113 12. Synchronous Serial Interface (SIO) 12.3 Function TMP86CM72FG External SCK input Last-byte transfer External SCK input SCK pin SO pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIOS = "0" causes the SIO to stop transferring SIOS = "1" causes the SIO to start transferring. SIOS SIOS = "1" causes the SIO to start transferring. SIOF SEF Transmit data are written. INTSIO is accepted. (In the interrupt service routine, clear SIOS to "0" and check the TXERR flag.) TXF Transmit-data write INTSIO TXERR After confirmation of SIOF = "0", set SIOCR1 and SIOCR2 and then write the transmit data to SIOBUF. After confirmation of SIOF = "0", set the transfer data to SIOBUF. Figure 12-8 Transmit Mode Operation (where 3 bytes are transferred on an external source clock) Second last byte Last byte More pulses than a specified number of bytes occur. SCK pin A0 B7 B6 B5 B4 B3 B2 B1 B0 SIOS = "0" causes the SIO to stop transferring. SO pin SIOS SIOF SEF TXF INTSIO is accepted. SIOINH = "1" causes the flag to be cleared and forces the SIO to halt (be initialized). INTSIO TXERR The SIO is forced to halt because of SIOS = "0" and TXERR occurrence (SIOINH = "1"). Figure 12-9 Occurrence of Transmit Error (where, before the SIO is directed to stop transferring (SIOCR1 Note: When the SIO is running (SIOSR Page 114 TMP86CM72FG 12.3.3.3 Receive mode Receive mode is assumed by setting SIOCR1 (1) Causing the SIO to start receiving 1. Set the receive mode, serial clock rate, and transfer direction, respectively, in SIOCR1 (2) Causing the SIO to stop receiving 1. When as many data bytes as specified in SIOCR2 (3) Received-data read timing Before reading received data, be sure to make sure SIOBUF is full (SIOSR Note 1: Be sure to read, from SIOBUF, as many received data bytes as specified in SIOCR2 Page 115 12. Synchronous Serial Interface (SIO) 12.3 Function TMP86CM72FG SIOS = "0" causes the SIO to stop transferring. SIOS SIOF SEF SCK pin SI pin A7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 RXF All data bytes have been read from SIOBUF. INTSIO Clearing SIOS within the interrupt service routine Figure 12-10 SIOCR1 12.3.3.4 Receive error During operation on an external clock, the following case is detected as a receive error, causing the receive error flag (SIOSR Note: When the SIO is running on an external clock, it becomes impossible to read the content of the receive data buffer (SIOBUF) correctly if the SCK pin goes low before as many data bytes as specified in SIOCR2 Page 116 TMP86CM72FG Example :Example of setting the receive mode (receive mode, external clock, and 32-byte transfer) Port setting (It is necessary to set P15 as SOpin by port setting. LD DI LD LDW EI LD WAIT: TEST JRS START: LD LD LD INTSIO (INTSIO service routine): LD (SIOCR1), 00010111B : Receive data reading Checks a checksum or the like to see if the received data are normal. : LD END: (SIOCR1), 01010111B ; Forces the SIO to halt. ; End of transfer ; Directs the SIO to stop transferring. (SIOCR1), 00010111B (SIOCR2), 00011111B (SIOCR1), 10010111B ; Sets the receive mode, selects the direction of transfer, and sets a serial clock. ; Sets the number of bytes to transfer. ; Directs the SIO to start transferring. (SIOCR1), 01******B (SIOSR). 7 F, WAIT (INTSEL),*0******B (EIRL), ******1********0B (TC3SBI),**0*****B ) ; IMF 0 ; INTSIO Select ; Enables INTSIO (EF9) ; Enables interrupts. ; Initializes the SIO (Forces the SIO halt). ; Checks to see if the SIO has halted (SIOF = 0). ; Jumps to START if the SIO is already at a halt. External SCK input Last-byte transfer External SCK input SCK pin SI pin A7 A6 A0 B7 B6 B5 B4 B3 B2 B1 B0 SIOS = "0" causes the SIO to stop transferring. C7 C6 C5 C4 C3 C SIOS SIOS = "1" causes the SIO to start transferring. SIOS = "1" causes the SIO to start transferring. SIOF SEF All data have been read from SIOBUF. INTSIO is accepted. (In the interrupt service routine, clear SIOS to "0" and read data from SIOBUF, check a checksum or the like to see if the received data are normal, and sets SIOINH = "1".) After confirmation of SIOF = "0", set SIOCR1 and SIOCR2. Confirm SIOF = "0". RXF INTSIO RXERR Figure 12-11 Receive Mode Operation (where 2 bytes are transferred on an external source clock) Page 117 12. Synchronous Serial Interface (SIO) 12.3 Function TMP86CM72FG External SCK input Last-byte transfer SCK pin SI pin A7 A6 A0 B7 B6 B5 B4 B3 B2 B1 B0 SIOS = "0" causes the SIO to stop transferring. SIOS SIOS = "1" causes the SIO to start transferring. SIOF SEF SIOINH = "1" causes the flag to be cleared and forces the SIO to halt (be initialized). RXF INTSIO INTSIO is accepted. (In the interrupt service routine, clear SIOS to "0" and read data from SIOBUF, check a checksum or the like to see if the received data are normal, and sets SIOINH = "1".) RXERR After confirmation of SIOF = "0" set SIOCR1 and SIOCR2. Figure 12-12 Occurrence of Receive Error (2 bytes are transferred on an external source clock) Note 1: When the SIO is running (SIOSR 12.3.3.5 Transmit/receive mode Transmit/receive mode is assumed by setting SIOCR1 (1) Causing the SIO to start transmitting/receiving 1. Set the transmit/receive mode, serial clock rate, and transfer direction, respectively, in SIOCR1 Note 1: SIOCR2 Page 118 TMP86CM72FG (2) Causing the SIO to stop transmitting/receiving 1. When as many data bytes as specified in SIOCR2 (3) Received-data read and transmit-data set timing After as many bytes as specified in SIOCR2 |